1. Field of the Invention
The present invention relates to a microprocessor and debug system having a function of tracing a program counter and a function of externally notifying that a preset address or data has been accessed.
2. Description of the Prior Art
FIG. 1 shows a debug system called an in-circuit emulator according to a prior art.
The system includes a user target system 500 and a debugger 505 for debugging the target system 500. The target system 500 has a microprocessor 501, a memory 503, and an I/O unit 502. The debugger 505 has a debugging microprocessor 506 and a monitor program memory 507.
To debug the target system 500, the microprocessor 501 is removed or disabled, and probes of the debugger 505 are connected to the place of the microprocessor 501 so that the microprocessor 506 may operate instead of the microprocessor 501. The microprocessor 506 executes a monitor program stored in the memory 507, to control a user program stored in the memory 503.
The microprocessor 506 executes the user program, accesses data in the memory 503, and accesses the I/O unit 502. The debugger 505 has a trace memory 508, so that the microprocessor 506 may provide trace information about an internal state such as the value of a program counter that is usually not provided by the microprocessor 501 through a processor bus 504.
The prior art of FIG. 1, however, must connect the debugger 505 to all pins of the microprocessor 501 of the target system 500. The microprocessor 501 has, for example, 70 pins for 30 address signals, four byte-enable signals, a read signal, a write signal, a read acknowledge signal, a write acknowledge signal, and 32 data signals. The debugger 505 must have probes for these pins, and therefore, is expensive and unstable. The microprocessor 506 must switch buses from one to another to access the memory 503 of the target system 500 and the memory 507 of the debugger 505, and therefore, is not applicable to a high-speed microprocessor.
If the target microprocessor has peripheral elements, it may have a different pin arrangement. In this case, the debugger must have probes proper for such a pin arrangement. When connected to the target system 500, the probes of the debugger 505 may influence and destabilize signals in the target system 500.
FIG. 2 shows a debug system called a ROM monitor according to another prior art.
A user target system 510 has a serial interface 512 connected to a host computer 517. A memory 513 stores a monitor program 514. A microprocessor 511 executes the monitor program 514 to access the memory 513, an I/O unit 515, and a register 516. A software break instruction is used to execute and control a user program.
This prior art employs the user memory 513 to store the monitor program 514. If the memory system of the target system 510 is imperfect, the monitor program 514 itself will be unstable. If the capacity of the memory 513 is small, there will be no space to store the monitor program 514. Since a monitor mode is started by a user interrupt, some program may not be debugged. The serial interface 512 mounted on the target system 510 is imperative for debugging but is useless after debugging. The debugging performance of this prior art is poor because it has no hardware break point and because it is incapable of tracing a program counter.
FIG. 3 shows a debug system according to still another prior art.
A user target system 520 has a microprocessor 521, which incorporates a serial interface 526 and a sequencer 525. The serial interface 526 communicates with a debug tool 529. The debug tool 529 sends signals to the interface 526, and the sequencer 525 interprets the signals. In response to the signals, the sequencer 525 temporarily stops the execution of a user program, accesses a register 528, uses a bus controller 527 to access an I/O unit 523 and a memory 524, and controls the user program. The serial interface 526 is usually incapable of directly communicating with a host computer 530. Accordingly, the debug tool 529 converts a command from the host computer 530 into a signal understandable by the microprocessor 521, and a signal from the microprocessor 521 into a data format understandable by the host computer 530.
The microprocessor 521 incorporates the sequencer 525, which must access the microprocessor 521 as well as the debug tool 529. In this way, this prior art employs a complicated connection logic to increase a chip area. If the target system 520 is provided with an additional register, the sequencer 525 must be modified accordingly through a complicated work. This prior art is incapable of tracing a program counter.
As explained above, the prior arts are incapable of tracing a program counter, or even if they can, they must connect many signals between a debug processor and a target system through a processor bus. According to the prior art of FIG. 1, the microprocessor 506 of the debugger 505 must access the memory 503 and I/O unit 502 of the target system 500, and it is difficult to control the timing of these access operations.
The prior art of FIG. 2 stores a monitor program in the user memory 513, to reduce a user memory space. Debugging by this prior is unsure and insufficient.
The prior art of FIG. 3 incorporates the sequencer 525 in the microprocessor 521 of the target system 520, to interpret and execute signals sent from the debug tool 529. Namely, this prior art involves a complicated connection between a target system and a debug tool. If it is required to modify the microprocessor 521, the sequencer 525 must also be modified through a complicated work.
The prior arts of FIGS. 2 and 3 have no trigger function. The prior art of FIG. 1 may have the trigger function in the debugging microprocessor 506 but with additional signals for providing trigger information.